View ADG1413YRUZ-REEL7_1207197.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Technical Data
FEATURES
2 Max On Resistance 0.5 Max On Resistance Flatness 200mA continuous current per channel 33 V supply range Fully specified at +12 V, 15 V, 5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead LFCSP Typical power consumption: <0.03 W
2 Max On Resistance, 15 V/12 V/5 V iCMOSTM Quad SPST Switch ADG1411/ADG1412/ADG1413
FUNCTIONAL BLOCK DIAGRAM
S1 IN1 D1 S2 IN2 IN2 D2 S3 IN3 D3 S4 IN4 D4 IN4 D4 IN3 D3 S4 IN4 D4 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 S1 IN1 D1 S2 D2 S1
ADG1411
ADG1412
ADG1413
S3
APPLICATIONS
Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems Relay Replacement
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Figure 1.
iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The ADG1411/ADG1412/ADG1413 contain four independent single-pole/single-throw (SPST) switches. The ADG1411 and ADG1412 differ only in that the digital control logic is inverted. The ADG1411 switches are turned on with Logic 0 on the appropriate control input, while Logic 1 is required for the ADG1412. The ADG1413 has two switches with digital control logic similar to that of the ADG1411; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG1413 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
GENERAL DESCRIPTION
The ADG1411/ADG1412/ADG1413 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an iCMOS process. iCMOS (industrial CMOS) is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. 2 Max On Resistance over temperature. Minimum distortion 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <0.03 W. 16-lead TSSOP and 4 mm x 4 mm LFCSP packages.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2007 Analog Devices, Inc. All rights reserved.
ADG1411/ADG1412/ADG1413 TABLE OF CONTENTS
Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8
Preliminary Technical Data
Terminology .......................................................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 13 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 16
REVISION HISTORY
Rev. PrE | Page 2 of 17
Preliminary Technical Data SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) -40C to +85C -40C to +125C VDD to VSS 1.5 2 0.1 0.5 0.1 0.5 0.01 0.5 0.01 0.5 Channel On Leakage, ID, IS (On) 0.04 1 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tON tOFF Break-Before-Make Time Delay, tD (ADG1413 only) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 2.5 5 V typ max typ max typ max nA typ nA max nA typ nA max nA typ
ADG1411/ADG1412/ADG1413
VS = 10 V, IS = -10 mA; Figure 20 VDD = +13.5 V, VSS = -13.5 V VS = 10 V , IS = -10 mA
VS = -5 V/0 V/+5 V; IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V; Figure 21 VS = 10V, VD = 10 V; Figure 21
2.5
5
VS = VD = 10 V; Figure 22
5
5
2.0 0.8 2.5 0.5
nA max
0.005 2.5 105 125 40 50 25 50 50 60 0.015 200 35 35 150
V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ
VIN = VINL or VINH
185 60 10
RL = 300 , CL = 35 pF VS = +10 V; Figure 23 RL = 300 , CL = 35 pF VS = +10 V; Figure 23 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; Figure 24 VS = 0 V, RS = 0 , CL = 1 nF; Figure 25 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 110 , 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 28 Vs = 0 V, f = 1 MHz Vs = 0 V, f = 1 MHz Vs = 0 V, f = 1 MHz
POWER REQUIREMENTS IDD IDD
0.001 1 220
Rev. PrE | Page 3 of 17
A typ A max A typ
VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V
ADG1411/ADG1412/ADG1413
25C ISS
VDD/VSS
Preliminary Technical Data
-40C to +85C -40C to +125C 320 1.
4.5/16.5
0.001
A max A typ A max
V min/max
Digital inputs = 0 V, 5V or VDD
Gnd = 0V
1
Guaranteed by design, not subject to production test.
Rev. PrE | Page 4 of 17
Preliminary Technical Data
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
Y Version -40C to +85C Unit -40C to +125C 0 V to VDD 2 3 0.1 4 V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max
V min/max
ADG1411/ADG1412/ADG1413
Test Conditions/Comments
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tON tOFF Break-Before-Make Time Delay, tD (ADG1413 only) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD IDD
VDD
VS = +10 V, IS = -10 mA; Figure 20 VDD = +10.8 V, VSS = 0 V VS = +10 V, IS = -10 mA
0.1 0.01 0.5 0.01 0.5 0.04 1
VS = -5 V/0 V/+5 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/0 V; Figure 21 VS = 1 V/10 V, VD = 10 V/0 V; Figure 21 VS = VD = 1 V or 10 V; Figure 22
2.5 2.5 5
5 5 5 2.0 0.8
0.001 0.5 3 120 155 45 65 50 50 50 60 0.015 200 35 35 150 0.001 1 220 320
5/16.5
VIN = VINL or VINH
225 85 10
RL = 300 , CL = 35 pF VS = 8 V; Figure 23 RL = 300 , CL = 35 pF VS = 8 V; Figure 23 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; Figure 24 VS = 6 V, RS = 0 , CL = 1 nF; Figure 25 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 110 , 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 28 Vs = 6V, f = 1 MHz Vs = 6V, f = 1 MHz Vs = 6V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V
Gnd = 0V, Vss = 0V
1
Guaranteed by design, not subject to production test.
Rev. PrE | Page 5 of 17
ADG1411/ADG1412/ADG1413
DUAL SUPPLY
VDD = 5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 tON tOFF Break-Before-Make Time Delay, tD (ADG1413 only) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD ISS
VDD/VSS
Preliminary Technical Data
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ nA typ
Test Conditions/Comments
3 4 0.1
VS = 3.3V, IS = -10 mA; Figure 20 VDD = +4.5 V, VSS = -4.5 V VS = 3.3 V , IS = -10 mA
0.1 0.01 0.5 0.01 0.5 0.04 1 2.5 2.5 5 5 5 5 2.0 0.8 0.001 0.5 3 120 155 45 65 50 10 50 60 0.015 200 35 35 150 0.001 1.0 0.001 1.0
4.5/16.5
VS = -3 V/0 V/+3 V; IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; Figure 21 VS = 4.5V, VD = 4.5 V; Figure 21 VS = VD = 4.5V; Figure 22
nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max
V min/max
VIN = VINL or VINH
225 85 10
RL = 300 , CL = 35 pF VS = 3 V; Figure 23 RL = 300 , CL = 35 pF VS = 3 V; Figure 23 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; Figure 24 VS = 0V, RS = 0 , CL = 1 nF; Figure 25 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 110 , 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 28 Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz VDD = 5.5 V , Vss = -5.5V Digital inputs = 0 V or VDD Digital inputs = 5 V
Gnd = 0V
1
Guaranteed by design, not subject to production test.
Rev. PrE | Page 6 of 17
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance 16-Lead LFCSP, JA Thermal Impedance Reflow Soldering Peak Temperature, Pb free
1
ADG1411/ADG1412/ADG1413
Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 300 mA (pulsed at 1 ms, 10% duty cycle max) 200 mA -40C to +125C -65C to +150C 150C 150.4C/W 72.7C/W 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrE | Page 7 of 17
ADG1411/ADG1412/ADG1413 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
D1 IN1 IN2 D2
16 15 14 13
S1 1 Vss 2 Gnd 3 S4 4
ADG1411 ADG1412 ADG1413
TOP VIEW (Not to Scale)
12 S2 11 Vdd 10 NC 9 S3
IN1 1 D1 2 S1 3 VSS 4 GND 5 D4 7 IN4 8
16 IN2 15 D2
5
6
7
8
D4 IN4 IN3 D3
12 NC TOP VIEW S4 6 (Not to Scale) 11 S3 10 D3 9 IN3
ADG1411 ADG1412 ADG1413
14 S2 13 VDD
EXPOSED PAD TIED TO SUBSTRATE, Vss NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin No. LFCSP 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 Description Logic Control Input. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Logic Control Input. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input.
Table 6. ADG1411/ADG1412 Truth Table
ADG1411 INx 0 1 ADG1412 INx 1 0 Switch Condition On Off
Table 7. ADG1413 Truth Table
Logic - INx 0 1 Switch 1, 4 Off On Switch 2, 3 On Off
Rev. PrE | Page 8 of 17
Preliminary Technical Data TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground.
ADG1411/ADG1412/ADG1413
CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON The delay between applying the digital control input and the output switching on. See Figure 23. tOFF The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental.
Rev. PrE | Page 9 of 17
ADG1411/ADG1412/ADG1413 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
Figure 5. On Resistance as a Function of VD (VS) for Single Supply
Figure 8. Leakage Currents as a Function of Temperature, Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply
Figure 9. Leakage Currents as a Function of Temperature, Single Supply
Rev. PrE | Page 10 of 17
Preliminary Technical Data
ADG1411/ADG1412/ADG1413
Figure 10. Logic Threshold Voltage vs. Supply Voltage
Figure 13. TON/TOFF Times vs. Temperature
Figure 11. IDD vs. Logic Level
Figure 14. Off Isolation vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Figure 15. Crosstalk vs. Frequency
Rev. PrE | Page 11 of 17
ADG1411/ADG1412/ADG1413
Preliminary Technical Data
Figure 16. On Response vs. Frequency
Figure 18. Capacitance vs. Source Voltage, Single Supply
Figure 19. THD + N vs. Frequency Figure 17. Capacitance vs. Source Voltage, Dual Supply
Rev. PrE | Page 12 of 17
Preliminary Technical Data TEST CIRCUITS
IDS V1 S D
04778-0-020
ADG1411/ADG1412/ADG1413
IS (OFF) A VS S D
ID (OFF) A
04778-0-021
ID (ON) NC S D A VD
04778-0-022
VS
RON = V1/IDS
VD
NC = No Connect
Figure 20. On Resistance
Figure 21. Off Leakage
Figure 22. On Leakage
VDD 0.1F
VSS 0.1F VIN VOUT VIN RL 300V GND CL 35pF VOUT
ADG1211
50%
50%
VDD S VS
VSS D
ADG1212
50% 90%
50% 90%
04778-0-023
IN
tON
tOFF
Figure 23. Switching Times
VDD 0.1F
VSS 0.1F VIN 0V 50% 50%
VDD VS1 VS2 S1 S2
VSS D1 D2 RL 300V CL 35pF VOUT2 RL 300V CL 35pF VOUT1 VOUT1 0V
90%
90%
VOUT2 0V
90%
90%
GND
tD
Figure 24. Break-Before-Make Time Delay
VDD
VSS
VDD RS S
VSS D VOUT CL 1nF GND
VIN
ADG1212
ON OFF
VS
IN
VIN VOUT
ADG1211
QINJ = CL3 DVOUT
04778-0-025
DVOUT
Figure 25. Charge Injection
Rev. PrE | Page 13 of 17
04778-0-024
IN1, IN2
ADG1213
tD
ADG1411/ADG1412/ADG1413
VDD 0.1F VSS 0.1F NETWORK ANALYZER
Preliminary Technical Data
VDD 0.1F VSS 0.1F NETWORK ANALYZER
VDD S IN
VSS
VDD S
VSS
50 D
50 VS VOUT
50 VS D VOUT
IN
VIN GND
RL 50
VIN GND
04778-0-026
RL 50
OFF ISOLATION = 20 LOG
VOUT VS
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 26. Off Isolation
Figure 28. Bandwidth
VDD 0.1F NETWORK ANALYZER VOUT RL 50
VSS 0.1F
VDD 0.1F
VSS 0.1F AUDIO PRECISION
VDD S1
VSS
VDD S
VSS RS
D S2 VS GND
R 50
IN D VIN GND RL 600 VOUT
VS V p-p
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT VS
Figure 27. Channel-to-Channel Crosstalk
04778-0-027
Figure 29.. THD + Noise
Rev. PrE | Page 14 of 17
04779-0-030
04778-0-028
Preliminary Technical Data OUTLINE DIMENSIONS
5.10 5.00 4.90
ADG1411/ADG1412/ADG1413
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 29. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.00 BSC SQ
0.60 MAX 0.60 MAX
13 12 16 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC
PIN 1 INDICATOR
TOP VIEW
0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
EXPOSED PAD
(BOTTOM VIEW)
9 8 5
4
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 30. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
Rev. PrE | Page 15 of 17
ADG1411/ADG1412/ADG1413
ORDERING GUIDE
Model ADG1411YRUZ1 ADG1411YRUZ-REEL1 ADG1411YRUZ-REEL71 ADG1411YCPZ-500RL71 ADG1411YCPZ-REEL71 ADG1412YRUZ1 ADG1412YRUZ-REEL1 ADG1412YRUZ-REEL71 ADG1412YCPZ-500RL71 ADG1412YCPZ-REEL71 ADG1413YRUZ1 ADG1413YRUZ-REEL1 ADG1413YRUZ-REEL71 ADG1413YCPZ-500RL71 ADG1413YCPZ-REEL71
1
Preliminary Technical Data
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (VQ_LFCSP) Lead Frame Chip Scale Package (VQ_LFCSP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (VQ_LFCSP) Lead Frame Chip Scale Package (VQ_LFCSP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (VQ_LFCSP) Lead Frame Chip Scale Package (VQ_LFCSP) Package Option RU-16 RU-16 RU-16 CP-16-4 CP-16-4 RU-16 RU-16 RU-16 CP-16-4 CP-16-4 RU-16 RU-16 RU-16 CP-16-4 CP-16-4
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Z = Pb-free part.
Rev. PrE | Page 16 of 17
Preliminary Technical Data NOTES
ADG1411/ADG1412/ADG1413
(c) 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06615-0-5/07(PrE)
Rev. PrE | Page 17 of 17

▲Up To Search▲

Price & Availability of ADG1413YRUZ-REEL7

	To Download ADG1413YRUZ-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .